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VIS (Verification Interacting with Synthesis) is a system for formal verification, synthesis, and simulation of finite state systems.

VIS provides the following features:

  • Simulation of logic circuits (proof of concept only).
  • Formal "implementation" verification of combinational and sequential circuits (proof of concept only).
  • State-of-the-art formal "design" verification using fair CTL model checking and language emptiness.
  • Logic synthesis via hierarchy restructuring and a path to and from SIS.

Current Version:   1.2

License Type:   ??

Home Site:

Source Code Availability:   Yes (fill out the feedback form at the Home Site above)

Available Binary Packages:

  • Debian Package:   No
  • RedHat RPM Package:   No
  • Other Packages:   No

Targeted Platforms:

Sun4 (SunOS), Solaris, DEC-Alpha, DEC-Mips, HP-UX, Linux, Windows95

Software/Hardware Requirements:


Other Links:

Mailing Lists/USENET News Groups:

All the questions about the software can be sent to

User Comments:

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