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Yalsim is a fast, hierarchical, logic timing simulator. It can be extended using the user-supplied circuit feature. It has its own hardware description language which is non standard. This may be one of its best and worst features. The parser for the language is very robust and could possibly be modified to support other more standard languages. It could possibly be a model for someone hoping to write a VHDL parser.

The interface is now through a graphical interface written using Tcl/Tk/Expectk.

Current Version:   Alpha 2

License Type:   Almost free for individuals, non-profit use

Home Site: (yalsim.tar.gz)

Source Code Availability:   Yes

Available Binary Packages:

  • Debian Package:   No
  • RedHat RPM Package:   No
  • Other Packages:   No

Targeted Platforms:

UNIX, Linux

Software/Hardware Requirements:


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