Ver Ver is a structural verilog compiler for UN*X operating systems. A stand alone simulator is also included for testing of logic designs. A cycle simulation compiler is also included which compiles netlists into fast C code.

Current Version:   1.2.33 License Type:   Free

Home Site: http://buster.nac.net/~bybell/ver/ver.html Source Code Availability:   Yes Available Binary Packages: Debian Package:   No RedHat RPM Package:   No Other Packages:   No Targeted Platforms: UN*X (NetBSD Amiga, Linux/PC, AIX) Software/Hardware Requirements: None

Other Links: http://metalab.unc.edu/pub/Linux/apps/circuits/ Mailing Lists/USENET News Groups: None User Comments: None See A Screen Shot? (Not Yet)

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