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VBS (Verilog Behavioral Simulator)

Simulator for Verilog HDL. Supports functions, tasks and module instantiation. Still lacks a lot of features, but this release has enough for a VLSI student to use and learn Verilog. Supports only behavioral constructs of Verilog and minimal simulation constructs such as 'initial' statements. This version has some additional features.

Current Version:   1.3.6

License Type:   GPL

Home Site:

Source Code Availability:   Yes

Available Binary Packages:

  • Debian Package:   No
  • RedHat RPM Package:   No
  • Other Packages:   Yes

Targeted Platforms:

C, C++, flex, bison

Software/Hardware Requirements:


Other Links: (vbs-*)

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