UDL/I UDL/I is a Register Transfer Level(RTL) HDL for describing spcification of a circuit to be synthesized. It was designed by UDL/I Language Committee in JEIDA independently from particular CAD tools:synthesizers or simulators. UDL/I is suitable for synchronous circuit design and also has language constructs to describe asynchronous circuit behavior. Explicit and clear semantics defintion is provided in UDL/I Language Reference Manual (LRM). A logic designer using UDL/I can easily understand behavior of a RTL description in UDL/I and predict a circuit to be synthesized. The UDL/I Simulation/Synthesis Environment consists of a UDL/I Compiler Simulator Logic Synthesizer.

Current Version:   1.1.6 License Type:   ??

Home Site: http://www.metsa.astem.or.jp/udli/ Source Code Availability:   Yes Available Binary Packages: Debian Package:   No RedHat RPM Package:   No Other Packages:   No Targeted Platforms: SunOS, and ported to Linux, FreeBSD, MachTen, HP-UX, IRIX Software/Hardware Requirements: 180-320MB disk space

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