SAL Home OTHERS Electrical & Related Software


TyVIS is a VHDL simulation kernel which has been implemented on top of WARPED, a general purpose Time Warp simulation kernel. This combination provides parallel VHDL simulation capability as WARPED allows sequential and parallel simulation. It is the designer's intent to have TyVIS be completely ignorant of the underlying simulation engine, as long as the engine provides TyVIS with the correct procedural interface. TyVIS allows you to simulate and execute VHDL code that has been translated into the TyVIS C++ intermediate form. The VHDL simulator provides the functionality required by a VHDL simulation kernel as specified by the VHDL LRM.

Current Version:   1.01

License Type:   GPL

Home Site:

Source Code Availability:   Yes

Available Binary Packages:

  • Debian Package:   No
  • RedHat RPM Package:   No
  • Other Packages:   No

Targeted Platforms:


Software/Hardware Requirements:


Other Links:

Mailing Lists/USENET News Groups:


User Comments:

  • None

See A Screen Shot? (Not Yet)

  SAL Home   |   Other Scientific Fields   |   Electrical & Related Software

Comments? SAL@KachinaTech.COM
Copyright © 1995-2001 by Herng-Jeng Jou
Copyright © 1997-2001 by Kachina Technologies, Inc.
All rights reserved.