TauSim is a synchronous Verilog simulator with support for X and Z values. Release 3.0 optimizes RTL code, achieving
high simulation speed on very large designs while preserving the rapid compilation of release 2.3. Gates and transistors are
also optimized, with gate level designs simulating at speeds similar to RTL.
TauSim is highly optimized for large Verilog designs with fast compilation, efficient memory utilization, and high simulation speed.
Current Version: 3.0
License Type: Commercial
Source Code Availability: No
Available Binary Packages:
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