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Super FinSim

Super FinSim is a powerful and robust Verilog simulation environment. It supports the entire Verilog Hardware Design Language including all behavioral, gate and switch level constructs, user defined primitives, specify blocks, system tasks and functions, PLI 1.0, VCD and SDF. Super FinSim is highly compatible with the industry's golden simulator, Verilog-XL.

Super FinSim is a mixed event driven and cycle based simulator and supports compiled, interpreted and any mixture of compiled and interpreted simulation. This powerful environment allows designers to leverage between the fast simulation speed of a compiled simulator and the fast turnaround time of an interpreter.

Current Version:   4.5

License Type:   Commercial

Home Site:

Source Code Availability:   No

Available Binary Packages:

  • Debian Package:   No
  • RedHat RPM Package:   No
  • Other Packages:   ??

Targeted Platforms:

Sun, SGI, DEC, HP, DEC, IBM PowerPC, Son NEWS, Windows 95/NT, Linux/i386. Detail at

Software/Hardware Requirements:

386 CPU or higher, 8MB RAM mininum, 40MB disk space

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