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EASE is a graphical HDL entry tool. It offers:

  • Graphical design environment with automated generation of hierarchical VHDL or Verilog code
  • Push-button import of legacy Verilog or VHDL designs and extraction of graphical hierarchy
  • Adheres to state of the art Windows look and feel for intuitive operation
  • Standards compliant (IEEE-1076-87&93 VHDL and IEEE-1364 Verilog)
  • True multi-user design environment and associated version control, managed by a sophisticated design environment browser
  • Extensive documentation capabilities
  • Integrates smoothly with the industry's most popular simulators and synthesis tools
  • Platform independent database
  • Integrated HDL language editor
  • Hot error reporting

Current Version:   ??

License Type:   Commercial

Home Site:

Source Code Availability:   No

Available Binary Packages:

  • Debian Package:   No
  • RedHat RPM Package:   No
  • Other Packages:   ??

Targeted Platforms:

Sun Sparc Solaris, HP HP-UX, PC/Windows 95/98/NT, PC/Linux

Software/Hardware Requirements:

16MB disk space, 32MB system RAM recommended

Other Links:

Mailing Lists/USENET News Groups:


User Comments:

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