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Cynlib is a C++ class library for higher-level hardware design using cynthesis. Cynlib provides the vocabulary for hardware modelling in C++. It is a set of C++ classes which implement many of the features found in the Verilog and VHDL hardware description languages. We call it a "Verilog-dialect" of C++, but it is more correct to say that it is a class library which implements many of the Verilog semantic features. The purpose of this library is to create a C/C++ environment in which hardware can be modelled and simulated.

Cynlib is intended to provide an environment in C++ for designing electronic hardware. Our goal is to give the designer the tools to do a complete hardware design in C++ without having to use traditional hardware description languages.

Current Version:   ??

License Type:   OpenSource License modified from Mozilla Public License

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Source Code Availability:   Yes

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C++ compiler

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